B0103034 陳建華 2015/10/28 硬體描述 (MUX 三位元多工器(2+1))

module top;

wire [2:0] OUT,A,B; 

wire SEL;

system_clock #6400 clock1(SEL);

system_clock #3200 clock2(A[2]);

system_clock #1600 clock3(A[1]);

system_clock #800 clock4(A[0]);

system_clock #400 clock5(B[2]);

system_clock #200 clock6(B[1]);

system_clock #100 clock7(B[0]);

mux2 mux_2(OUT[2:1], A[2:1], B[2:1], SEL);

mux mux_1 (OUT[0], A[0], B[0], SEL);

endmodule 

module mux2(OUT, A, B, SEL);

output [1:0] OUT; 

input [1:0] A, B; 

input SEL; 

mux hi (OUT[1], A[1], B[1], SEL);

mux lo (OUT[0], A[0], B[0], SEL);

endmodule

module mux(OUT, A, B, SEL);

output OUT; 

input A, B, SEL;

and a1(sel_a, A, SEL);

not a2(sel_n, SEL);

and a3(sel_b, sel_n, B);

or a4(OUT, sel_a, sel_b);

endmodule 

module system_clock(clk); 

parameter PERIOD=100; 

output clk; 

reg clk; 

initial clk=0; 

always 

 begin 

#(PERIOD/2) clk=~clk; 

 end 

always@(posedge clk)

 if($time>8000)$stop; 

endmodule