B0103034 陳建華 2015/12/16 硬體描述 期中考

module top;

wire A, B, C, D, F;

system_clock #800 clock1(A);

system_clock #400 clock2(B);

system_clock #200 clock3(C);

system_clock #100 clock4(D);

nand S1(a, A, A);

nand S2(b, B, B);

nand S3(c, C, C);

nand S4(d, D, D);

nand C1(F1, A, D, b, c);

nand C2(F2, B, c, d);

nand C3(F3, A, B, d);

nand C4(F4, A, B, C); 

nand C5(F5, B, C, d); 

nand C6(F6, C, a, d); 

nand o1(F, F1, F2, F3, F4, F5, F6);

endmodule

module system_clock(clk);

parameter PERIOD=100;

output clk;

reg clk;

initial clk=0;

always

 begin

#(PERIOD/2) clk=~clk;

 end

always@(posedge clk)

 if($time>1000)$stop;

B0103034 陳建華 2015/12/2 硬體描述 A~D F(nand)

module top;

wire A, B, C, D, F;

system_clock #800 clock1(A);

system_clock #400 clock2(B);

system_clock #200 clock3(C);

system_clock #100 clock4(D);

nand n1(a_n, A, A);

nand n2(b_n, B, B);

nand n3(c_n, C, C);

nand n4(d_n, D, D);

nand a11(F1, C, D);

nand a12(F5, F1, F1);

nand a21(F2, a_n, b_n, D);

nand a22(F6, F2, F2);

nand a31(F3, B, c_n, d_n);

nand a32(F7, F3, F3);

nand a41(F4, A, c_n, d_n);

nand a42(F8, F4, F4);

nand a5(O1, F5, F5);

nand a6(O2, F6, F6);

nand a7(O3, F7, F7);

nand a8(O4, F8, F8);

nand o1(F, O1, O2, O3, O4);

endmodule

module system_clock(clk);

parameter PERIOD=100;

output clk;

reg clk;

initial clk=0;

always

 begin

#(PERIOD/2) clk=~clk;

 end

always@(posedge clk)

 if($time>1000)$stop;

endmodule

B0103034 陳建華 2015/12/2 硬體描述 A~D F(and.or.not)

module top;

wire A, B, C, D, F;

system_clock #800 clock1(A);

system_clock #400 clock2(B);

system_clock #200 clock3(C);

system_clock #100 clock4(D);

not n1(a_n, A);

not n2(b_n, B);

not n3(c_n, C);

not n4(d_n, D);

and a1(F1, C, D);

and a2(F2, a_n, b_n, D);

and a3(F3, B, c_n, d_n);

and a4(F4, A, c_n, d_n);

or  o1(F, F1, F2, F3, F4);

endmodule

module system_clock(clk);

parameter PERIOD=100;

output clk;

reg clk;

initial clk=0;

always

 begin

#(PERIOD/2) clk=~clk;

 end

always@(posedge clk)

 if($time>1000)$stop;

endmodule

B0103034 陳建華 2015/11/25 硬體描述 三位元全加法器 行為

module fulladder (sum, c_out, a, b, c_in);

wire s1, c1, c2;

output sum;

output c_out;

input a, b, c_in;

assign{c_out,sum}=a+b+c_in;

endmodule

module adder3(sum, c_out, a, b, c_in);

wire [2:0] c; 

output [2:0] sum;

output c_out;

input [2:0] a;

input [2:0] b;

input c_in;

fulladder fa1(sum[0], c[1], a[0], b[0], c_in) ;

fulladder fa2(sum[1], c[2], a[1], b[1], c[1]) ;

fulladder fa3(sum[2], c_out, a[2], b[2], c[2]) ;

endmodule

module main;

reg [2:0] a;

reg [2:0] b;

wire [2:0] sum;

wire c_out;

adder3 DUT (sum, c_out, a, b, 1'b0);

initial

begin

  a = 4'b0101;

  b = 4'b0000;

end

always #50 begin

  b=b+1;

  $monitor("%dns monitor: a=%d b=%d sum=%d", $stime, a, b, sum);

end

initial #2000 $finish;

endmodule

B0103034 陳建華 2015/11/25 硬體描述 三位元全加法器 延伸

module top;

wire Cin,A1,B1,A2,B2,A3,B3,Cout1,Cout2,Cout3,Sum1,Sum2,Sum3;

system_clock #6400 clock1(Cin);

system_clock #3200 clock1(A3);

system_clock #1600 clock1(B3);

system_clock #800 clock1(A2);

system_clock #400 clock1(B2);

system_clock #200 clock2(A1);

system_clock #100 clock3(B1);

adder1 M1(Cin,A1,B1,A2,B2,A3,B3,Cout1,Cout2,Cout3,Sum1,Sum2,Sum3);

endmodule

module adder1(Cin,A1,B1,A2,B2,A3,B3,Cout1,Cout2,Cout3,Sum1,Sum2,Sum3);

output Cout1,Sum1,Cout2,Cout3,Sum2,Sum3;

input A1,B1,A2,B2,A3,B3,Cin;

and I1 (A1andB1, A1, B1);

xor I2 (A1xorB1, A1, B1);

and I3 (And1, A1xorB1, Cin);

or I4 (Cout1, A1andB1, And1);

xor I5 (Sum1, A1xorB1, Cin);

and I6 (A2andB2, A2, B2);

xor I7 (A2xorB2, A2, B2);

and I8 (And2, A2xorB2, Cout1);

or I9 (Cout2, A2andB2, And2);

xor I10 (Sum2, A2xorB2, Cout1);

and I11 (A3andB3, A3, B3);

xor I12 (A3xorB3, A3, B2);

and I13 (And3, A3xorB3, Cout2);

or I14 (Cout3, A3andB3, And3);

xor I15 (Sum3, A3xorB3, Cout2);

endmodule

module system_clock(clk);

parameter PERIOD=100;

output clk;

reg clk;

initial clk=0;

always

begin

#(PERIOD/2) clk=~clk;

end

always@(posedge clk)

if($time>100000)$stop;

endmodule

B0103034 陳建華 2015/11/25 硬體描述 三位元全加法器

module fulladder (sum, c_out, a, b, c_in);

wire s1, c1, c2;

output sum;

output c_out;

input a, b, c_in;

xor xo1(s1, a, b);

xor xo2(sum, s1, c_in);

and a1(c1, a,b);

and a2(c2, s1, c_in) ;

xor xo3(c_out, c2, c1) ;

endmodule

module adder3(sum, c_out, a, b, c_in);

wire [2:0] c;

output [2:0] sum;

output c_out;

input [2:0] a;

input [2:0] b;

input c_in;

fulladder fa1(sum[0], c[1], a[0], b[0], c_in) ;

fulladder fa2(sum[1], c[2], a[1], b[1], c[1]) ;

fulladder fa3(sum[2], c_out, a[2], b[2], c[2]) ;

endmodule

module main;

reg [2:0] a;

reg [2:0] b;

wire [2:0] sum;

wire c_out;

adder3 DUT (sum, c_out, a, b, 1'b0);

initial

begin

  a = 4'b0101;

  b = 4'b0000;

end

always #50 begin

  b=b+1;

  $monitor("%dns monitor: a=%d b=%d sum=%d", $stime, a, b, sum);

end

initial #2000 $finish;

endmodule

B0103034 陳建華 2015/11/18 硬體描述 一位元全加法器 XOR

module top;

wire A, B, Cin, Cout, Sum;
system_clock #400 clock1(Cin);
system_clock #200 clock2(A);
system_clock #100 clock3(B);


xor xo1(OUT1, A, B);
xor xo2(Sum, OUT1, Cin);
and a1 (OUT2, OUT1, Cin);
and a2 (OUT3, A, B);
or  o1 (Cout, OUT2, OUT3);

endmodule

module system_clock(clk);
parameter PERIOD=100;
output clk;
reg clk;

initial clk=0;

always
 begin
#(PERIOD/2) clk=~clk;
 end

always@(posedge clk)
 if($time>1000)$stop;

endmodule