B0103034 陳建華 2015/12/16 硬體描述 期中考

module top;

wire A, B, C, D, F;

system_clock #800 clock1(A);

system_clock #400 clock2(B);

system_clock #200 clock3(C);

system_clock #100 clock4(D);

nand S1(a, A, A);

nand S2(b, B, B);

nand S3(c, C, C);

nand S4(d, D, D);

nand C1(F1, A, D, b, c);

nand C2(F2, B, c, d);

nand C3(F3, A, B, d);

nand C4(F4, A, B, C); 

nand C5(F5, B, C, d); 

nand C6(F6, C, a, d); 

nand o1(F, F1, F2, F3, F4, F5, F6);

endmodule

module system_clock(clk);

parameter PERIOD=100;

output clk;

reg clk;

initial clk=0;

always

 begin

#(PERIOD/2) clk=~clk;

 end

always@(posedge clk)

 if($time>1000)$stop;

B0103034 陳建華 2015/12/2 硬體描述 A~D F(nand)

module top;

wire A, B, C, D, F;

system_clock #800 clock1(A);

system_clock #400 clock2(B);

system_clock #200 clock3(C);

system_clock #100 clock4(D);

nand n1(a_n, A, A);

nand n2(b_n, B, B);

nand n3(c_n, C, C);

nand n4(d_n, D, D);

nand a11(F1, C, D);

nand a12(F5, F1, F1);

nand a21(F2, a_n, b_n, D);

nand a22(F6, F2, F2);

nand a31(F3, B, c_n, d_n);

nand a32(F7, F3, F3);

nand a41(F4, A, c_n, d_n);

nand a42(F8, F4, F4);

nand a5(O1, F5, F5);

nand a6(O2, F6, F6);

nand a7(O3, F7, F7);

nand a8(O4, F8, F8);

nand o1(F, O1, O2, O3, O4);

endmodule

module system_clock(clk);

parameter PERIOD=100;

output clk;

reg clk;

initial clk=0;

always

 begin

#(PERIOD/2) clk=~clk;

 end

always@(posedge clk)

 if($time>1000)$stop;

endmodule

B0103034 陳建華 2015/12/2 硬體描述 A~D F(and.or.not)

module top;

wire A, B, C, D, F;

system_clock #800 clock1(A);

system_clock #400 clock2(B);

system_clock #200 clock3(C);

system_clock #100 clock4(D);

not n1(a_n, A);

not n2(b_n, B);

not n3(c_n, C);

not n4(d_n, D);

and a1(F1, C, D);

and a2(F2, a_n, b_n, D);

and a3(F3, B, c_n, d_n);

and a4(F4, A, c_n, d_n);

or  o1(F, F1, F2, F3, F4);

endmodule

module system_clock(clk);

parameter PERIOD=100;

output clk;

reg clk;

initial clk=0;

always

 begin

#(PERIOD/2) clk=~clk;

 end

always@(posedge clk)

 if($time>1000)$stop;

endmodule

B0103034 陳建華 2015/11/25 硬體描述 三位元全加法器 行為

module fulladder (sum, c_out, a, b, c_in);

wire s1, c1, c2;

output sum;

output c_out;

input a, b, c_in;

assign{c_out,sum}=a+b+c_in;

endmodule

module adder3(sum, c_out, a, b, c_in);

wire [2:0] c; 

output [2:0] sum;

output c_out;

input [2:0] a;

input [2:0] b;

input c_in;

fulladder fa1(sum[0], c[1], a[0], b[0], c_in) ;

fulladder fa2(sum[1], c[2], a[1], b[1], c[1]) ;

fulladder fa3(sum[2], c_out, a[2], b[2], c[2]) ;

endmodule

module main;

reg [2:0] a;

reg [2:0] b;

wire [2:0] sum;

wire c_out;

adder3 DUT (sum, c_out, a, b, 1'b0);

initial

begin

  a = 4'b0101;

  b = 4'b0000;

end

always #50 begin

  b=b+1;

  $monitor("%dns monitor: a=%d b=%d sum=%d", $stime, a, b, sum);

end

initial #2000 $finish;

endmodule

B0103034 陳建華 2015/11/25 硬體描述 三位元全加法器 延伸

module top;

wire Cin,A1,B1,A2,B2,A3,B3,Cout1,Cout2,Cout3,Sum1,Sum2,Sum3;

system_clock #6400 clock1(Cin);

system_clock #3200 clock1(A3);

system_clock #1600 clock1(B3);

system_clock #800 clock1(A2);

system_clock #400 clock1(B2);

system_clock #200 clock2(A1);

system_clock #100 clock3(B1);

adder1 M1(Cin,A1,B1,A2,B2,A3,B3,Cout1,Cout2,Cout3,Sum1,Sum2,Sum3);

endmodule

module adder1(Cin,A1,B1,A2,B2,A3,B3,Cout1,Cout2,Cout3,Sum1,Sum2,Sum3);

output Cout1,Sum1,Cout2,Cout3,Sum2,Sum3;

input A1,B1,A2,B2,A3,B3,Cin;

and I1 (A1andB1, A1, B1);

xor I2 (A1xorB1, A1, B1);

and I3 (And1, A1xorB1, Cin);

or I4 (Cout1, A1andB1, And1);

xor I5 (Sum1, A1xorB1, Cin);

and I6 (A2andB2, A2, B2);

xor I7 (A2xorB2, A2, B2);

and I8 (And2, A2xorB2, Cout1);

or I9 (Cout2, A2andB2, And2);

xor I10 (Sum2, A2xorB2, Cout1);

and I11 (A3andB3, A3, B3);

xor I12 (A3xorB3, A3, B2);

and I13 (And3, A3xorB3, Cout2);

or I14 (Cout3, A3andB3, And3);

xor I15 (Sum3, A3xorB3, Cout2);

endmodule

module system_clock(clk);

parameter PERIOD=100;

output clk;

reg clk;

initial clk=0;

always

begin

#(PERIOD/2) clk=~clk;

end

always@(posedge clk)

if($time>100000)$stop;

endmodule

B0103034 陳建華 2015/11/25 硬體描述 三位元全加法器

module fulladder (sum, c_out, a, b, c_in);

wire s1, c1, c2;

output sum;

output c_out;

input a, b, c_in;

xor xo1(s1, a, b);

xor xo2(sum, s1, c_in);

and a1(c1, a,b);

and a2(c2, s1, c_in) ;

xor xo3(c_out, c2, c1) ;

endmodule

module adder3(sum, c_out, a, b, c_in);

wire [2:0] c;

output [2:0] sum;

output c_out;

input [2:0] a;

input [2:0] b;

input c_in;

fulladder fa1(sum[0], c[1], a[0], b[0], c_in) ;

fulladder fa2(sum[1], c[2], a[1], b[1], c[1]) ;

fulladder fa3(sum[2], c_out, a[2], b[2], c[2]) ;

endmodule

module main;

reg [2:0] a;

reg [2:0] b;

wire [2:0] sum;

wire c_out;

adder3 DUT (sum, c_out, a, b, 1'b0);

initial

begin

  a = 4'b0101;

  b = 4'b0000;

end

always #50 begin

  b=b+1;

  $monitor("%dns monitor: a=%d b=%d sum=%d", $stime, a, b, sum);

end

initial #2000 $finish;

endmodule

B0103034 陳建華 2015/11/18 硬體描述 一位元全加法器 XOR

module top;

wire A, B, Cin, Cout, Sum;
system_clock #400 clock1(Cin);
system_clock #200 clock2(A);
system_clock #100 clock3(B);


xor xo1(OUT1, A, B);
xor xo2(Sum, OUT1, Cin);
and a1 (OUT2, OUT1, Cin);
and a2 (OUT3, A, B);
or  o1 (Cout, OUT2, OUT3);

endmodule

module system_clock(clk);
parameter PERIOD=100;
output clk;
reg clk;

initial clk=0;

always
 begin
#(PERIOD/2) clk=~clk;
 end

always@(posedge clk)
 if($time>1000)$stop;

endmodule

B0103034 陳建華 2015/11/18 硬體描述 一位元全加法器

module test_adder1;

 reg a,b;

 reg carry_in ; 

 wire sum;

 wire carry_out;

 adder1_behavorial A1(carry_out, sum, a, b, carry_in);

 initial 

  begin

    carry_in = 0; a = 0; b = 0; 

    # 100 if ( carry_out != 0 | sum !== 0) 

                $display(" 0+0+0=00 sum is WRONG!");

              else

                $display(" 0+0+0=00 sum is RIGHT!");

    carry_in = 0; a = 0; b = 1; 

    # 100 if ( carry_out != 0 | sum !== 1) 

               $display(" 0+0+1=01 sum is WRONG!");

              else

               $display(" 0+0+1=01 sum is RIGHT!");

    carry_in = 0; a = 1; b = 0; 

    # 100 if ( carry_out != 0 | sum !== 1) 

               $display(" 0+1+0=01 sum is WRONG!");

              else

               $display(" 0+1+0=01 sum is RIGHT!");

    carry_in = 0; a = 1; b = 1; 

    # 100 if ( carry_out != 1 | sum !== 0) 

                $display(" 0+1+1=10 sum is WRONG!");

              else

                $display(" 0+1+1=10 sum is RIGHT!");

    carry_in = 1; a = 0; b = 0; 

    # 100 if ( carry_out != 0 | sum !== 1) 

               $display(" 1+0+0=01 sum is WRONG!");

              else

               $display(" 1+0+0=01 sum is RIGHT!");

     carry_in = 1; a = 0; b = 1; 

    # 100 if ( carry_out != 1 | sum !== 0) 

                $display(" 1+0+1=10 sum is WRONG!");

              else

                $display(" 1+0+1=10 sum is RIGHT!");

    carry_in = 1; a = 1; b = 0; 

    # 100 if ( carry_out != 1 | sum !== 0) 

               $display(" 1+1+0=10 sum is WRONG!");

              else

               $display(" 1+1+0=10 sum is RIGHT!");

    carry_in = 1; a = 1; b = 1; 

    # 100 if ( carry_out != 1 | sum !== 1) 

               $display(" 1+1+1=11 sum is WRONG!");

              else

               $display(" 1+1+1=11 sum is RIGHT!");

    $finish;

  end

endmodule

module adder1_behavorial (carry_out, sum, a, b, carry_in);

 input a, b, carry_in;

 output carry_out, sum;

  assign sum = (~a&b&~carry_in)|(~carry_in&a&~b)|(a&b&carry_in)|(~a&~b&carry_in);

  assign carry_out = a&carry_in|a&b|b&carry_in; 

endmodule

B0103034 陳建華 2015/11/4 硬體描述 (A1.A0.B1.B0.SEL)[for 迴圈]

module top;

  integer is;

  integer ia[1:0],ib[1:0];

  reg [1:0]a,b;

  reg s;

  wire [1:0]out;

  mux_behavioral mux2(out,a,b,s);

  initial

    begin

      for (is=0; is<=1; is = is + 1)

       begin

        s = is;

         for (ia[0]=0; ia[0]<=1; ia[0] = ia[0]+1)

          begin

           a[0]= ia[0];

            for (ia[1]=0; ia[1]<=1; ia[1] = ia[1]+ 1)

             begin

              a[1] = ia[1];

               for (ib[0]=0; ib[0]<=1; ib[0] = ib[0]+1)

                 begin

                   b[0] = ib[0];

                    for (ib[1]=0; ib[1]<=1; ib[1] = ib[1]+ 1)

                     begin

                      b[1] = ib[1];

                 #1 $display("a[0]=%d a[1]=%d b[0]=%d b[1]=%d s=%d out[0]%d out[1]%d",a[0],a[1],b[0],b[1],s,out[0],out[1]);

                      end

                    end

                  end

              end

         end

    end

endmodule

module mux_behavioral(OUT,A,B,SEL);

 output [1:0]OUT;

 input [1:0] A,B;

 input SEL;

mux1 X1(OUT[0],A[0],B[0],SEL);

mux1 X2(OUT[1],A[1],B[1],SEL);

endmodule

module mux1(OUT, A, B, SEL);

 output OUT;

 input A,B,SEL;

 not n1(NOT_SEL, SEL);

 and a1 (SEL_A, A, NOT_SEL);

 and a2 (SEL_B, SEL, B);

 or  o1 (OUT, SEL_A, SEL_B);

endmodule

B0103034 陳建華 2015/11/4 硬體描述 (A,sel,B) [for 迴圈]

module top;

  integer ia,ib,is;

  reg  a,b,s;

  wire out;

  mux_behavioral mux1(out,a,b,s);

  initial

    begin

      for (is=0; is<=1; is = is+1)

        begin

          s = is;

          for (ia=0; ia<=1; ia = ia + 1)

            begin

              a = ia;

              for (ib=0; ib<=1; ib = ib + 1)

               begin

                 b = ib;

                 #20 $display("a=%d b=%d s=%d out=%d",a,b,s,out);

               end

            end

        end

    end

endmodule

module mux_behavioral(OUT, A, B, SEL);

 output OUT;

 input A,B,SEL;

 wire  A,B,SEL;

 reg    OUT;

  always @(A or B or SEL)

   OUT = (A & ~SEL)|(B & SEL );

endmodule

module system_clock(clk); 

parameter PERIOD=100; 

output clk; 

reg clk; 

initial clk=0; 

always 

 begin 

#(PERIOD/2) clk=~clk; 

 end 

always@(posedge clk)

 if($time>1000)$stop; 

endmodule 

B0103034 陳建華 2015/10/28 硬體描述 (MUX 三位元多工器(2+1))

module top;

wire [2:0] OUT,A,B; 

wire SEL;

system_clock #6400 clock1(SEL);

system_clock #3200 clock2(A[2]);

system_clock #1600 clock3(A[1]);

system_clock #800 clock4(A[0]);

system_clock #400 clock5(B[2]);

system_clock #200 clock6(B[1]);

system_clock #100 clock7(B[0]);

mux2 mux_2(OUT[2:1], A[2:1], B[2:1], SEL);

mux mux_1 (OUT[0], A[0], B[0], SEL);

endmodule 

module mux2(OUT, A, B, SEL);

output [1:0] OUT; 

input [1:0] A, B; 

input SEL; 

mux hi (OUT[1], A[1], B[1], SEL);

mux lo (OUT[0], A[0], B[0], SEL);

endmodule

module mux(OUT, A, B, SEL);

output OUT; 

input A, B, SEL;

and a1(sel_a, A, SEL);

not a2(sel_n, SEL);

and a3(sel_b, sel_n, B);

or a4(OUT, sel_a, sel_b);

endmodule 

module system_clock(clk); 

parameter PERIOD=100; 

output clk; 

reg clk; 

initial clk=0; 

always 

 begin 

#(PERIOD/2) clk=~clk; 

 end 

always@(posedge clk)

 if($time>8000)$stop; 

endmodule 

B0103034 陳建華 2015/10/28 硬體描述 (MUX 四位元多工器(2+2))

module top;

wire [3:0] OUT,A,B; 

wire SEL;

system_clock #25600 clock1(SEL);

system_clock #12800 clock2(A[3]);

system_clock #6400 clock3(A[2]);

system_clock #3200 clock4(A[1]);

system_clock #1600 clock5(A[0]);

system_clock #800 clock6(B[3]);

system_clock #400 clock7(B[2]);

system_clock #200 clock8(B[1]);

system_clock #100 clock9(B[0]);

mux2 hi(OUT[3:2], A[3:2], B[3:2], SEL);

mux2 lo(OUT[1:0], A[1:0], B[1:0], SEL);

endmodule 

module mux2(OUT, A, B, SEL);

output [1:0] OUT; 

input [1:0] A, B; 

input SEL; 

mux hi (OUT[1], A[1], B[1], SEL);

mux lo (OUT[0], A[0], B[0], SEL);

endmodule

module mux(OUT, A, B, SEL);

output OUT; 

input A, B, SEL;

and a1(sel_a, A, SEL);

not a2(sel_n, SEL);

and a3(sel_b, sel_n, B);

or a4(OUT, sel_a, sel_b);

endmodule

module system_clock(clk); 

parameter PERIOD=100; 

output clk; 

reg clk; 

initial clk=0; 

always 

 begin 

#(PERIOD/2) clk=~clk; 

 end 

always@(posedge clk)

 if($time>30000)$stop; 

endmodule 

B0103034 陳建華 2015/10/21 硬體描述 (MUX 三位元多工器)

B0103034 陳建華 2015/10/14 硬體描述 (MUX)

B0103034 陳建華 2015/10/14 硬體描述 (A1.A0.B1.B0.SEL)

B0103034 陳建華 2015/10/7 硬體描述 (A,sel,B)

B0103034 陳建華 2015/10/7 硬體描述 (A~F)

B0103034 陳建華 2015/9/30 硬體描述 and(a1 a2) or (b1)

B0103034 陳建華 2015/9/30 硬體描述 and(a1) or (b1)

B0103034 陳建華 2015/9/30 硬體描述 and(a1 a2)

B0103034 陳建華 2015/9/23 硬體描述