B0103034 陳建華 2015/11/18 硬體描述 一位元全加法器 XOR

module top;

wire A, B, Cin, Cout, Sum;
system_clock #400 clock1(Cin);
system_clock #200 clock2(A);
system_clock #100 clock3(B);


xor xo1(OUT1, A, B);
xor xo2(Sum, OUT1, Cin);
and a1 (OUT2, OUT1, Cin);
and a2 (OUT3, A, B);
or  o1 (Cout, OUT2, OUT3);

endmodule

module system_clock(clk);
parameter PERIOD=100;
output clk;
reg clk;

initial clk=0;

always
 begin
#(PERIOD/2) clk=~clk;
 end

always@(posedge clk)
 if($time>1000)$stop;

endmodule