B0103034 陳建華 2015/12/16 硬體描述 期中考

module top;

wire A, B, C, D, F;

system_clock #800 clock1(A);

system_clock #400 clock2(B);

system_clock #200 clock3(C);

system_clock #100 clock4(D);

nand S1(a, A, A);

nand S2(b, B, B);

nand S3(c, C, C);

nand S4(d, D, D);

nand C1(F1, A, D, b, c);

nand C2(F2, B, c, d);

nand C3(F3, A, B, d);

nand C4(F4, A, B, C); 

nand C5(F5, B, C, d); 

nand C6(F6, C, a, d); 

nand o1(F, F1, F2, F3, F4, F5, F6);

endmodule

module system_clock(clk);

parameter PERIOD=100;

output clk;

reg clk;

initial clk=0;

always

 begin

#(PERIOD/2) clk=~clk;

 end

always@(posedge clk)

 if($time>1000)$stop;