B0103034 陳建華 2015/12/2 硬體描述 A~D F(and.or.not)

module top;

wire A, B, C, D, F;

system_clock #800 clock1(A);

system_clock #400 clock2(B);

system_clock #200 clock3(C);

system_clock #100 clock4(D);

not n1(a_n, A);

not n2(b_n, B);

not n3(c_n, C);

not n4(d_n, D);

and a1(F1, C, D);

and a2(F2, a_n, b_n, D);

and a3(F3, B, c_n, d_n);

and a4(F4, A, c_n, d_n);

or  o1(F, F1, F2, F3, F4);

endmodule

module system_clock(clk);

parameter PERIOD=100;

output clk;

reg clk;

initial clk=0;

always

 begin

#(PERIOD/2) clk=~clk;

 end

always@(posedge clk)

 if($time>1000)$stop;

endmodule