B0103034 陳建華 2015/12/2 硬體描述 A~D F(nand)

module top;

wire A, B, C, D, F;

system_clock #800 clock1(A);

system_clock #400 clock2(B);

system_clock #200 clock3(C);

system_clock #100 clock4(D);

nand n1(a_n, A, A);

nand n2(b_n, B, B);

nand n3(c_n, C, C);

nand n4(d_n, D, D);

nand a11(F1, C, D);

nand a12(F5, F1, F1);

nand a21(F2, a_n, b_n, D);

nand a22(F6, F2, F2);

nand a31(F3, B, c_n, d_n);

nand a32(F7, F3, F3);

nand a41(F4, A, c_n, d_n);

nand a42(F8, F4, F4);

nand a5(O1, F5, F5);

nand a6(O2, F6, F6);

nand a7(O3, F7, F7);

nand a8(O4, F8, F8);

nand o1(F, O1, O2, O3, O4);

endmodule

module system_clock(clk);

parameter PERIOD=100;

output clk;

reg clk;

initial clk=0;

always

 begin

#(PERIOD/2) clk=~clk;

 end

always@(posedge clk)

 if($time>1000)$stop;

endmodule